1. Field of the Invention
The present invention relates to a dividing device which is incorporated in a digital arithmetic device and executes a division on input, normalized divisor data and dividend data so as to produce a 2-bit partial quotient in each cycle.
2. Description of the Related Art
In recent years, the progress of the semiconductor technologies has enabled more than millions of transistors to be integrated in a single chip. Now it is common to incorporate many blocks each having a very complex arithmetic function in a single VLSI. Also digital arithmetic devices incorporate various kinds of units such as a fixed-point adder, subtracter, multiplier, and divider, and a logical operation unit as well as a floating-point adder, subtracter, multiplier, and divider. The technologies are advancing not only in the degree of integration but also in processing speed, which is becoming increasingly high.
In such digital arithmetic devices, dividing devices to be incorporated in VLSIs are generally classified into two types: the first type executes a convergence-type division by repetitive multiplications, and the second type executes a subtraction/shift-type division. The first type dividing device, which needs a multiplier, can be implemented with almost no increase in hardware if a VLSI incorporates a multiplier. However, in this type of dividing device, it is difficult to increase the processing speed. If a VLSI incorporates no multiplier, a multiplier needs to be provided for the division, which will cause a problem in hardware cost. On the other hand, although the second type of dividing device can increase the processing speed to a certain extent by increasing the amount of hardware, the processing speed cannot be increased in a simple manner.
Examples of subtraction/shift-type dividing devices are described in Kai Hwang: "Computer Arithmetic Principles, Architecture, and Design."